Multi-Rate PHY / Framer for Data Networks (TXC-06412B)


Your Superior Choice for Aggregating Access Data Traffic

The PHAST®-12P is a highly integrated SONET/SDH overhead termination device designed for ATM or PPP packet applications which can terminate a single STM-4/OC-12 line or four STM-1/OC-3 lines. Clock synthesis and clock recovery for these lines are incorporated. The device provides regeneration/section and multiplexer/line overhead processing, high order (VC-3/VC-4/VC-4Xc/STS-1/STS-3c/STS-6c/STS-9c/STS-12c) pointer tracking and retiming, and SPE path overhead processing and performance monitoring. It is a powerful solution for OC-12 and multi-OC-3 data applications, especially those requiring critical complex protection capability. PHAST-12P also provides a full 36 x 36 non-blocking STS-1 level cross connect, allowing line/path (UPSR/SNCP) protection. An APS line port may be utilized for applications such as MSP 1+1, 1:1, and 1:n architectures.

The PHAST®-12P is designed to interface directly with the ASPEN Express® Packet/ATM switching device for data access applications. The software driver contains independent modules that allow the user to compile only relevant required components, a considerable resource savings. The function of the API’s driver is to configure, control and manage the PHAST®-12P device as well as collect and deliver fault and performance monitoring data to the host.

PHAST is a Registered Trademark of TranSwitch Corporation

Application Diagram

TranSwitch IP Communications, Multicore Processor


  • 376-lead plastic ball grid array (PBGA) package (23 mm x 23 mm)
  • + 3.3V and +1.8V power supplies, 5V tolerant digital I/O leads
  • Boundary scan and line loopback
  • Software device driver is provided
  • 16-bit wide microprocessor interface, selectable between Motorola or Intel
  • TOH and POH access port
  • Ring Ports for line/path ring applications
  • MS/Line or RS/Section DCC access port per line
  • POS-PHY Level 2 16-bit interface at 50 MHz
  • UTOPIA Level 2 16-bit interface at 50 MHz
  • PPP packet handling
  • ATM cell handling
  • High order path cross-connect with VC-3/STS-1 granularity
  • Complete high order path overhead processing at VC-3/VC-4/VC-4-Xc/STS-1/STS-3c/STC-6c/STS-9c/STS-12c SPE level
  • Complete RS/section and MS/line overhead processing
  • Supports 1+1, 1:1 and 1:n APS using a serial port interface
  • Bit-serial LVDS 622.08 Mbit/s APS port
  • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis
    • single 622.08 Mbit/s STM-4/OC-12 signal or
    • four 155.52 Mbit/s STM-1/OC-3 signals


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