STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator (TXC-06103)
Summary
The TranSwitch PHAST®-3N (TXC-06103) is an STM-1/STS-3/STS-3c section, line and path overhead termination device that provides a terminal side Telecom Bus interface. The PHAST®-3N device provides either a serial or parallel interface on the line side. The serial interface provides 155 MHz clock recovery and clock synthesis. Line and section overhead bytes are processed. The PHAST®-3N performs pointer tracking, and receive and transmit pointer justification. The PHAST®-3N also performs POH byte processing. TOH (RSOH and MSOH) and POH bytes are written into RAM locations for microprocessor access or provided via interfaces for external access. In the transmit direction, the PHAST®-3N will either interface to downstream timing or provide the timing signals. The transmit POH bytes can be inserted from RAM, a serial POH interface, a mate PHAST®-3N device for path and line ring applications, or directly from the terminal side.
The PHAST®-3N can generate line and path AIS in the receive and transmit directions. For testing, the device provides boundary scan, a PRBS generator and analyzer, B2 and B3 byte BER measurements, programmable BIP error mask generation, line and terminal loopback, and STS-1 terminal loopback. The device provides either Motorola or Intel microprocessor access. Performance counters can be configured to be saturating or roll-over. The interrupts, with mask bits, can be programmed for activation on positive, negative or positive and negative alarm transitions, or positive levels. A software polling register is also provided.
PHAST is a Registered Trademark of TranSwitch Corporation
Application Diagram
Features
- 256-lead, 27 mm x 27 mm, plastic ball grid array package
- Single +3.3 volt, ±5% power supply; 5 volt tolerant inputs
- Boundary scan, loopbacks, and optional PRBS generator/detector
- Motorola or Intel microprocessor interface for memory access
- Receive and transmit line/path AIS generation
- Receive pointer tracking
- AIS, LOP, NDF and false pointer detection
- Receive and transmit pointer rejustification to receive and transmit reference clock and frame pulse
- Pointer leak register control
- PJ and NJ justification counters
- Bypass option
- Telecom Bus terminal interface source timing mode
- Transmit timing for downstream devices from reference clock and frame pulse
- Optional V1 pulse
- Tributary unequipped/AIS generation for TUG-3, TU-2/VT6, TU-12/VT2 and TU-11/VT1.5
- Telecom Bus terminal interface
- Clock, byte data, parity, C1J1V1, SPE, POH byte, AIS indication, bus active indication
- Interfaces
- TOH (RSOH & MSOH) bytes with programmable marker pulse
- K1/K2 APS bytes, E1 and E2 order wire bytes
- Section data communication (D1-D3) bytes
- Line data communication (D4-D12) bytes
- POH bytes (for VC-4 or each STS-1)
- Alarm Indication Port (AIP) for line/path ring operation
- Scan and drive leads (two each)
- N1 byte tandem connection processing with TIM (ETSI) or optional data link access (ANSI)
- Supports 1+1 or 1:N APS applications
- Section, line and path overhead byte insertion
- From RAM, interfaces, terminal, ring (mate device) or receive side (e.g., RDI)
- Section, line, and path overhead byte processing
- RAM access for overhead bytes
- Line AIS, REI (FEBE) and RDI detection
- B2 and B3 byte BIP detection with BER measurement
- J0 byte TIM or single-byte comparison
- S1 byte change in synchronization status
- J1 byte TIM or 64-byte LF/CR alignment
- C2 byte PSL, unequipped, PDI detection
- G1 byte RDI (single-bit or three-bit), path REI (FEBE) detection
- H4 byte multiframe detection with optional V1 pulse generation
- Byte-parallel SDH/SONET line interface
- Parity detection/generation with optional framing pulse input
- Bit-serial SDH/SONET line interface
- Pseudo-ECL interface with clock recovery and synthesis
Diagram
