PHAST®-6P

Dual OC-3/STM-1 SONET/SDH Overhead Terminator, Cell & Packet with APS (TXC-06406)

Summary

The Phast®-6P is a highly integrated SONET/SDH overhead termination device designed for ATM or PPP packet applications which can terminate two OC-3/STM-1/OC-3 lines. Clock synthesis and clock recovery for these lines are incoporated. The device provides regenerator section and multiplex section (line) overhead processing, high-order (VC-3/VC-4/STS-1/STS-3c) pointer trackeing and retiming, and SPE path overhead processing and performance monitoring. It is a powerful solution for single or dual OC-3 data applications, especially those requiring critical complex protection capability. PHAST®-6P also provides a full 18×18 non-blocking STS-1 level cross connect, allowing line/path (UPSR/SNCP) protection. An APS line port may be utilized for applications such as MSP 1+1, 1:1, and 1:n architectures.

The PHAST®-6P is designed to interface directly with the ASPEN Express® Packet/ATM switching device, EnvoyTM-2GE or DiplomatTM A for data access applications. The software driver contains independent modules that allow the user to compile only relevent required components, a considerable resource savings. The function of the API’s driver is to configure, control and manage the PHAST®-6P device as well as collect and deliver fault and performance monitoring data to the host.


Application Diagram

TranSwitch IP Communications, Multicore Processor

Features

  • Hardware: Bit-serial Line
  • Hardware: Integrated Clock, Data Recovery, Clock Synthesis
  • Hardware: 1+1, 1:1 and 1:n APS for two OC-3/STM-1 Signals
  • Hardware: TOH, POH Processing, Generation Functions
  • Hardware: High-order Pointer Tracker/Retiming, Performance Monitor
  • Hardware: Dedicated Overhead Byte Interface
  • Hardware: High-order Cross Connect (VC-3/STS-1/STM-0 Level)
  • Hardware: High-order Path and Line Loopbacks
  • Software: API-based Device Driver
  • Data Path: UTOPIA/POS-PHY Level 2
  • Data Path: Line and Path Alarm Indication Ports
  • Microprocessor: Intel/Motorola Compatible (16-Bit Data)
  • Other: JTAG Boundary Scan (IEEE JTAG™)

 

Diagram

TranSwitch IP Communications, Multicore Processor

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