TEMx28®

Integrated Dual-Bus T1/E1 28 Channel Mapper (TXC-04222)

Summary

The TEMx28® device is designed for add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. Up to 28 E1, DS1, or VT/TU payloads are mapped to and from VT1.5/TU-11s and VT2/TU-12s carried in an STM-1 VC-4 or STS-3 format. The device interfaces to a multiple-segment, byte-parallel SDH/SONET-formatted bus at the 19.44 Mbit/s byte rate. The E1 and DS1 signals can be HDB3 or B8ZS/AMI rail signals, or NRZ signals. The VT/TU interface can be provided with or without the overhead bytes for virtual concatenation applications. The TEMx28® performs pointer tracking and overhead byte processing, including single-bit or 3-bit RDI operation, and optional tandem connection capability. All overhead bytes, including the V1/V2/V4 bytes, are provided for microprocessor access.

The TEMx28® can generate receive and transmit line AIS, transmit unequipped and supervisory unequipped channels, and transmit VT/TU AIS, in addition to standards-compliant overhead byte monitoring. For testing, the device provides IEEE 1149.1 boundary scan, a PRBS generator and analyzer, and both line and facility loopbacks. The TEMx28® supports split bus access for either Intel or Motorola microprocessors. Its performance counters can be configured to be either saturating or roll over. Interrupts can be generated by alarms that latch on positive, negative, or both positive and negative status transitions, and they can be disabled via mask bits. A software polling register and summary alarm bit status are also provided. One second measurements are performed for alarms and counters.

TEMx28 is a Registered Trademark of TranSwitch Corporation


Application Diagram

TranSwitch IP Communications, Multicore Processor

Features

  • 376-lead plastic ball grid array package (23 x 23 mm)
  • Single +3.3 V power supply, 5 V tolerant I/O leads
  • IEEE 1149.1 standard boundary scan
  • One second measurements: counters and alarms
  • Polling registers and global summary alarm status
  • Line and facility loopbacks, generation of BIP-2 and REI errors, PRBS generator and analyzer per channel
  • Selectable positive, negative and positive/negative alarm transition interrupt options
  • Processor access to H1/H2, H4 overhead bytes, and V1/V2 and V4 bytes
  • J2 trail trace comparison option
  • Tandem connection capability per ETSI standards
  • Single-bit or 3-bit RDI operation per channel
  • Performance counters for pointer movements, BIP-2 errors, REI and coding violations
  • Drop buses are monitored for parity, loss of clock, and upstream AIS
  • Digital desynchronizer
  • H4 multiframe option in place of Telecom Bus V1 pulse
  • Selectable HDB3/B8ZS/AMI positive/negative rail, NRZ, or VT/TU interfaces per channel
  • Cross connect applications (DS1 mapped to/from VT2/TU-12s)
  • Add bus and drop bus timing modes
  • Add/drop 21/28 E1, DS1, or VT/TU payloads from two add and two drop STM-1/VC4, STS-3 buses

 

Diagram

TranSwitch IP Communications, Multicore Processor

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